In the fabrication of ultra-large-scale integrated (ULSI) circuits, vertical stacking, or integration, of a plurality of metal wiring circuits, or metal layers, to form a multilevel structure has become an efficient way to improve circuit performance and increase the functional complexity of the circuits. The metal wiring circuits are connected by the so-called "vias", which are formed through a dielectric layer sandwiched by two adjacent metal layers.
Vias are formed typically by first forming through holes in the dielectric layer, followed by the deposition of a conductive material into the through holes. In order to improve the step coverage of a subsequent deposition process, especially a sputter deposition process, in the through hole that has been formed in a dielectric layer on top of a conductive layer, the through hole is often formed to have a funnel shape, i.e., a generally straight lower portion and a tapered portion radiating from the mouth of the straight lower portion. Such a funnel shaped through hole is typically formed using a so-called wet-by-dry etch process, by which the dielectric layer is etched using, simultaneously, a wet etch process and a dry etch process. The dry etch process, which is substantially anisotropic, forms a straight passageway in the dielectric layer. The wet etch process, which is substantially isotropic, causing the passageway to be widened in the direction substantially perpendicular to the dry etching direction. As the dry etch progresses, the extent of wet etch accumulates, and the accumulated extent of the wet etch decreases with increased depth into the dielectric, due to decreased wet etch time. Thus, the final result is a funnel shaped via (i.e., through hole) consisting of two sections, a dry etch (i.e., lower) section with a generally uniform width, and a wet etch (i.e., upper) section with a tapered or bowl-shaped width. The width of the wet etch upper section increases from the mouth (i.e., the intersection between the dry etch lower section and the wet etch upper section) to the top surface of the dielectric layer.
One of the disadvantages of the funnel-shaped vias formed with the conventional wet-by-dry process is that the tapered section has a very steep curve-up portion. This can substantially reduce the step coverage efficiency that the funnel-shaped vias are intended to provide. To maximize the step coverage efficiency in a subsequent sputter depositing process, the tapered section should be as smooth as possible, and the steep curve-up portion near the top of the via should be substantially reduced.
Another disadvantage of the funnel-shaped vias formed with the conventional wet-by-dry process is that there exist sharp angles between the dry etch section and the wet etch section, and between the via and the photoresist (which is the also the exit angle of the via at the top dielectric surface). The sharp exit angle is also related to the steep curve-up portion of the tapered section of the via discussed above. These sharp angles can cause some blind spots in the overall fabrication process and result in reduced production yield.
Due to the high degree of competition in the semiconductor industry, it is important to take careful looks at every possible way that may improve production yield. Preferably, such improvement is done in a cost-effective manner.